# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx ZynqMP clock controller

maintainers:
  - Michal Simek <michal.simek@amd.com>

description:
  The clock controller is a hardware block of Xilinx ZynqMP clock tree. It
  reads required input clock frequencies from the devicetree and acts as clock
  provider for all clock consumers of PS clocks.

properties:
  compatible:
    const: xlnx,zynqmp-clk
 
  "#clock-cells":
    const: 1

  clocks:
    description: List of clock specifiers which are external input
      clocks to the given clock controller.
    minItems: 5
    items:
      - description: PS reference clock
      - description: reference clock for video system
      - description: alternative PS reference clock
      - description: auxiliary reference clock
      - description: transceiver reference clock
      - description: (E)MIO clock source
      - description: GEM emio clock
      - description: Watchdog external clock

  clock-names:
    minItems: 5
    items:
      - const: pss_ref_clk
      - const: video_clk
      - const: pss_alt_ref_clk
      - const: aux_ref_clk
      - const: gt_crx_ref_clk
      - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$"
      - pattern: "gem[0-3]+_emio_clk.*$"
      - pattern: "swdt[0-1]+_ext_clk.*$"

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    clock-controller {
        compatible = "xlnx,zynqmp-clk";
        clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
                 <&aux_ref_clk>, <&gt_crx_ref_clk>;
        clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
                      "aux_ref_clk", "gt_crx_ref_clk";
        #clock-cells = <1>;
    };
...