Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller on SM4450 maintainers: - Ajit Pandey <quic_ajipan@quicinc.com> - Taniya Das <quic_tdas@quicinc.com> description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM4450 See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h properties: compatible: const: qcom,sm4450-gcc clocks: items: - description: Board XO source - description: Sleep clock source - description: UFS Phy Rx symbol 0 clock source - description: UFS Phy Rx symbol 1 clock source - description: UFS Phy Tx symbol 0 clock source - description: USB3 Phy wrapper pipe clock source required: - compatible - clocks - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,rpmh.h> clock-controller@100000 { compatible = "qcom,sm4450-gcc"; reg = <0x00100000 0x001f4200>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, <&usb_1_qmpphy>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; ... |