# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Clock and Reset Controller

maintainers:
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The Clock and Reset (CAR) is the HW module responsible for muxing and gating
  Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
 
  CLKGEN provides the registers to program the PLLs. It controls most of
  the clock source programming and most of the clock dividers.
 
  CLKGEN input signals include the external clock for the reference frequency
  (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
 
  Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
 
  RSTGEN provides the registers needed to control resetting of each block in
  the Tegra system.

properties:
  compatible:
    enum:
      - nvidia,tegra20-car
      - nvidia,tegra30-car
      - nvidia,tegra114-car
      - nvidia,tegra210-car

  reg:
    maxItems: 1
 
  '#clock-cells':
    const: 1
 
  "#reset-cells":
    const: 1

patternProperties:
  "^(sclk)|(pll-[cem])$":
    type: object
    properties:
      compatible:
        enum:
          - nvidia,tegra20-sclk
          - nvidia,tegra30-sclk
          - nvidia,tegra30-pllc
          - nvidia,tegra30-plle
          - nvidia,tegra30-pllm

      operating-points-v2: true

      clocks:
        items:
          - description: node's clock

      power-domains:
        maxItems: 1
        description: phandle to the core SoC power domain

    required:
      - compatible
      - operating-points-v2
      - clocks
      - power-domains

    additionalProperties: false

required:
  - compatible
  - reg
  - '#clock-cells'
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
 
    car: clock-controller@60006000 {
        compatible = "nvidia,tegra20-car";
        reg = <0x60006000 0x1000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
 
        sclk {
            compatible = "nvidia,tegra20-sclk";
            operating-points-v2 = <&opp_table>;
            clocks = <&tegra_car TEGRA20_CLK_SCLK>;
            power-domains = <&domain>;
        };
    };