Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: StarFive JH7110 System Clock and Reset Generator maintainers: - Emil Renner Berthing <kernel@esmil.dk> properties: compatible: const: starfive,jh7110-syscrg reg: maxItems: 1 clocks: oneOf: - items: - description: Main Oscillator (24 MHz) - description: GMAC1 RMII reference or GMAC1 RGMII RX - description: External I2S TX bit clock - description: External I2S TX left/right channel clock - description: External I2S RX bit clock - description: External I2S RX left/right channel clock - description: External TDM clock - description: External audio master clock - description: PLL0 - description: PLL1 - description: PLL2 - items: - description: Main Oscillator (24 MHz) - description: GMAC1 RMII reference - description: GMAC1 RGMII RX - description: External I2S TX bit clock - description: External I2S TX left/right channel clock - description: External I2S RX bit clock - description: External I2S RX left/right channel clock - description: External TDM clock - description: External audio master clock - description: PLL0 - description: PLL1 - description: PLL2 clock-names: oneOf: - items: - const: osc - enum: - gmac1_rmii_refin - gmac1_rgmii_rxin - const: i2stx_bclk_ext - const: i2stx_lrck_ext - const: i2srx_bclk_ext - const: i2srx_lrck_ext - const: tdm_ext - const: mclk_ext - const: pll0_out - const: pll1_out - const: pll2_out - items: - const: osc - const: gmac1_rmii_refin - const: gmac1_rgmii_rxin - const: i2stx_bclk_ext - const: i2stx_lrck_ext - const: i2srx_bclk_ext - const: i2srx_lrck_ext - const: tdm_ext - const: mclk_ext - const: pll0_out - const: pll1_out - const: pll2_out '#clock-cells': const: 1 description: See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. '#reset-cells': const: 1 description: See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. required: - compatible - reg - clocks - clock-names - '#clock-cells' - '#reset-cells' additionalProperties: false examples: - | clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x13020000 0x10000>; clocks = <&osc>, <&gmac1_rmii_refin>, <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, <&tdm_ext>, <&mclk_ext>, <&pllclk 0>, <&pllclk 1>, <&pllclk 2>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", "tdm_ext", "mclk_ext", "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; }; |