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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip Sparx5 DPLL Clock maintainers: - Lars Povlsen <lars.povlsen@microchip.com> description: | The Sparx5 DPLL clock controller generates and supplies clock to various peripherals within the SoC. properties: compatible: const: microchip,sparx5-dpll reg: maxItems: 1 clocks: maxItems: 1 '#clock-cells': const: 1 required: - compatible - reg - clocks - '#clock-cells' additionalProperties: false examples: # Clock provider for eMMC: - | lcpll_clk: lcpll-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <2500000000>; }; clks: clock-controller@61110000c { compatible = "microchip,sparx5-dpll"; #clock-cells = <1>; clocks = <&lcpll_clk>; reg = <0x1110000c 0x24>; }; ... |