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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek PCIESYS clock and reset controller description: The MediaTek PCIESYS controller provides various clocks to the system. maintainers: - Matthias Brugger <matthias.bgg@gmail.com> properties: compatible: enum: - mediatek,mt7622-pciesys - mediatek,mt7629-pciesys reg: maxItems: 1 "#clock-cells": const: 1 description: The available clocks are defined in dt-bindings/clock/mt*-clk.h "#reset-cells": const: 1 required: - reg - "#clock-cells" - "#reset-cells" additionalProperties: false examples: - | clock-controller@1a100800 { compatible = "mediatek,mt7622-pciesys"; reg = <0x1a100800 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; |