Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek Functional Clock Controller for MT8188 maintainers: - Garmin Chang <garmin.chang@mediatek.com> description: | The clock architecture in MediaTek like below PLLs --> dividers --> muxes --> clock gate The devices provide clock gate control in different IP blocks. properties: compatible: enum: - mediatek,mt8188-adsp-audio26m - mediatek,mt8188-camsys - mediatek,mt8188-camsys-rawa - mediatek,mt8188-camsys-rawb - mediatek,mt8188-camsys-yuva - mediatek,mt8188-camsys-yuvb - mediatek,mt8188-ccusys - mediatek,mt8188-imgsys - mediatek,mt8188-imgsys-wpe1 - mediatek,mt8188-imgsys-wpe2 - mediatek,mt8188-imgsys-wpe3 - mediatek,mt8188-imgsys1-dip-nr - mediatek,mt8188-imgsys1-dip-top - mediatek,mt8188-imp-iic-wrap-c - mediatek,mt8188-imp-iic-wrap-en - mediatek,mt8188-imp-iic-wrap-w - mediatek,mt8188-ipesys - mediatek,mt8188-mfgcfg - mediatek,mt8188-vdecsys - mediatek,mt8188-vdecsys-soc - mediatek,mt8188-vencsys - mediatek,mt8188-wpesys - mediatek,mt8188-wpesys-vpp0 reg: maxItems: 1 '#clock-cells': const: 1 required: - compatible - reg - '#clock-cells' additionalProperties: false examples: - | clock-controller@11283000 { compatible = "mediatek,mt8188-imp-iic-wrap-c"; reg = <0x11283000 0x1000>; #clock-cells = <1>; }; |