Based on kernel version 7.2. Page generated on 2026-08-20 08:41 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global North West and South East Clock & Reset Controller on Nord SoC maintainers: - Taniya Das <taniya.das@oss.qualcomm.com> description: | Qualcomm global clock control (NW, SE) module provides the clocks, resets and power domains on Nord SoC. See also: include/dt-bindings/clock/qcom,nord-nwgcc.h include/dt-bindings/clock/qcom,nord-segcc.h properties: compatible: enum: - qcom,nord-nwgcc - qcom,nord-segcc clocks: items: - description: Board XO source - description: Sleep clock source required: - compatible - clocks - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,rpmh.h> clock-controller@8b00000 { compatible = "qcom,nord-nwgcc"; reg = <0x08b00000 0xf4200>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; ... |