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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic DDR Clock Controller maintainers: - Martin Blumenstingl <martin.blumenstingl@googlemail.com> properties: compatible: enum: - amlogic,meson8-ddr-clkc - amlogic,meson8b-ddr-clkc reg: maxItems: 1 clocks: maxItems: 1 clock-names: items: - const: xtal "#clock-cells": const: 1 required: - compatible - reg - clocks - clock-names - "#clock-cells" additionalProperties: false examples: - | ddr_clkc: clock-controller@400 { compatible = "amlogic,meson8-ddr-clkc"; reg = <0x400 0x20>; clocks = <&xtal>; clock-names = "xtal"; #clock-cells = <1>; }; ... |