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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/apm,xgene-socpll-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: APM X-Gene SoC PLL, PCPPLL, and PMD clocks maintainers: - Khuong Dinh <khuong@os.amperecomputing.com> properties: compatible: items: - enum: - apm,xgene-pcppll-clock - apm,xgene-pcppll-v2-clock - apm,xgene-pmd-clock - apm,xgene-socpll-clock - apm,xgene-socpll-v2-clock reg: maxItems: 1 reg-names: items: - enum: [ csr-reg, div-reg ] - const: div-reg minItems: 1 clocks: maxItems: 1 clock-names: enum: [ pcppll, socpll ] "#clock-cells": const: 1 clock-output-names: maxItems: 1 required: - compatible - reg - clocks - '#clock-cells' - clock-output-names additionalProperties: false |