Based on kernel version 6.17. Page generated on 2025-10-03 10:03 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: APM X-Gene SoC device clocks maintainers: - Khuong Dinh <khuong@os.amperecomputing.com> properties: compatible: const: apm,xgene-device-clock reg: minItems: 1 maxItems: 2 reg-names: items: - enum: [ csr-reg, div-reg ] - const: div-reg minItems: 1 clocks: maxItems: 1 "#clock-cells": const: 1 clock-output-names: maxItems: 1 clock-names: maxItems: 1 csr-offset: description: Offset to the CSR reset register $ref: /schemas/types.yaml#/definitions/uint32 default: 0 csr-mask: description: CSR reset mask bit $ref: /schemas/types.yaml#/definitions/uint32 default: 0xf enable-offset: description: Offset to the enable register $ref: /schemas/types.yaml#/definitions/uint32 default: 8 enable-mask: description: CSR enable mask bit $ref: /schemas/types.yaml#/definitions/uint32 default: 0xf divider-offset: description: Offset to the divider register $ref: /schemas/types.yaml#/definitions/uint32 default: 0 divider-width: description: Width of the divider register $ref: /schemas/types.yaml#/definitions/uint32 default: 0 divider-shift: description: Bit shift of the divider register $ref: /schemas/types.yaml#/definitions/uint32 default: 0 required: - compatible - reg - clocks - '#clock-cells' - clock-output-names additionalProperties: false |