# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 Clock Control Unit Dividers

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description: |
  Clocks Control Unit is the core of Baikal-T1 SoC System Controller
  responsible for the chip subsystems clocking and resetting. The CCU is
  connected with an external fixed rate oscillator, which signal is transformed
  into clocks of various frequencies and then propagated to either individual
  IP-blocks or to groups of blocks (clock domains). The transformation is done
  by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
  later ones are described in this binding. Each clock domain can be also
  individually reset by using the domain clocks divider configuration
  registers. Baikal-T1 CCU is logically divided into the next components:
  1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
     in general can provide any frequency supported by the CCU PLLs).
  2) PLLs clocks generators (PLLs).
  3) AXI-bus clock dividers (AXI) - described in this binding file.
  4) System devices reference clock dividers (SYS) - described in this binding
     file.
  which are connected with each other as shown on the next figure:
 
          +---------------+
          | Baikal-T1 CCU |
          |   +----+------|- MIPS P5600 cores
          | +-|PLLs|------|- DDR controller
          | | +----+      |
  +----+  | |  |  |       |
  |XTAL|--|-+  |  | +---+-|
  +----+  | |  |  +-|AXI|-|- AXI-bus
          | |  |    +---+-|
          | |  |          |
          | |  +----+---+-|- APB-bus
          | +-------|SYS|-|- Low-speed Devices
          |         +---+-|- High-speed Devices
          +---------------+
 
  Each sub-block is represented as a separate DT node and has an individual
  driver to be bound with.
 
  In order to create signals of wide range frequencies the external oscillator
  output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
  then passed over CCU dividers to create signals required for the target clock
  domain (like AXI-bus or System Device consumers). The dividers have the
  following structure:
 
          +--------------+
  CLKIN --|->+----+ 1|\  |
  SETCLK--|--|/DIV|->| | |
  CLKDIV--|--|    |  | |-|->CLKLOUT
  LOCK----|--+----+  | | |
          |          |/  |
          |           |  |
  EN------|-----------+  |
  RST-----|--------------|->RSTOUT
          +--------------+
 
  where CLKIN is the reference clock coming either from CCU PLLs or from an
  external clock oscillator, SETCLK - a command to update the output clock in
  accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
  the output clock stabilization, EN - enable/disable the divider block,
  RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
  peculiarities the dividers may lack of some functionality depicted on the
  figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
  clock provider just doesn't expose either switching functions, or the rate
  configuration, or both of them.
 
  The clock dividers, which output clock is then consumed by the SoC individual
  devices, are united into a single clocks provider called System Devices CCU.
  Similarly the dividers with output clocks utilized as AXI-bus reference clocks
  are called AXI-bus CCU. Both of them use the common clock bindings with no
  custom properties. The list of exported clocks and reset signals can be found
  in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
  'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
  are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
  to be a children of later one.

if:
  properties:
    compatible:
      contains:
        const: baikal,bt1-ccu-axi

then:
  properties:
    clocks:
      items:
        - description: CCU SATA PLL output clock
        - description: CCU PCIe PLL output clock
        - description: CCU Ethernet PLL output clock

    clock-names:
      items:
        - const: sata_clk
        - const: pcie_clk
        - const: eth_clk

else:
  properties:
    clocks:
      items:
        - description: External reference clock
        - description: CCU SATA PLL output clock
        - description: CCU PCIe PLL output clock
        - description: CCU Ethernet PLL output clock

    clock-names:
      items:
        - const: ref_clk
        - const: sata_clk
        - const: pcie_clk
        - const: eth_clk

properties:
  compatible:
    enum:
      - baikal,bt1-ccu-axi
      - baikal,bt1-ccu-sys

  reg:
    maxItems: 1
 
  "#clock-cells":
    const: 1
 
  "#reset-cells":
    const: 1

  clocks: true

  clock-names: true

additionalProperties: false

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names

examples:
  # AXI-bus Clock Control Unit node:
  - |
    #include <dt-bindings/clock/bt1-ccu.h>
 
    clock-controller@1f04d030 {
      compatible = "baikal,bt1-ccu-axi";
      reg = <0x1f04d030 0x030>;
      #clock-cells = <1>;
      #reset-cells = <1>;
 
      clocks = <&ccu_pll CCU_SATA_PLL>,
               <&ccu_pll CCU_PCIE_PLL>,
               <&ccu_pll CCU_ETH_PLL>;
      clock-names = "sata_clk", "pcie_clk", "eth_clk";
    };
  # System Devices Clock Control Unit node:
  - |
    #include <dt-bindings/clock/bt1-ccu.h>
 
    clock-controller@1f04d060 {
      compatible = "baikal,bt1-ccu-sys";
      reg = <0x1f04d060 0x0a0>;
      #clock-cells = <1>;
      #reset-cells = <1>;
 
      clocks = <&clk25m>,
               <&ccu_pll CCU_SATA_PLL>,
               <&ccu_pll CCU_PCIE_PLL>,
               <&ccu_pll CCU_ETH_PLL>;
      clock-names = "ref_clk", "sata_clk", "pcie_clk",
                    "eth_clk";
    };
  # Required Clock Control Unit PLL node:
  - |
    ccu_pll: clock-controller@1f04d000 {
      compatible = "baikal,bt1-ccu-pll";
      reg = <0x1f04d000 0x028>;
      #clock-cells = <1>;
 
      clocks = <&clk25m>;
      clock-names = "ref_clk";
    };
...