Based on kernel version 6.13
. Page generated on 2025-01-21 08:20 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 | Alphascale Clock Controller The ACC (Alphascale Clock Controller) is responsible for choosing proper clock source, setting dividers and clock gates. Required properties for the ACC node: - compatible: must be "alphascale,asm9260-clock-controller" - reg: must contain the ACC register base and size - #clock-cells : shall be set to 1. Simple one-cell clock specifier format is used, where the only cell is used as an index of the clock inside the provider. It is encouraged to use dt-binding for clock index definitions. SoC specific dt-binding should be included to the device tree descriptor. For example Alphascale ASM9260: #include <dt-bindings/clock/alphascale,asm9260.h> This binding contains two types of clock providers: _AHB_ - AHB gate; _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider. All clock specific details can be found in the SoC documentation. CLKID_AHB_ROM 0 CLKID_AHB_RAM 1 CLKID_AHB_GPIO 2 CLKID_AHB_MAC 3 CLKID_AHB_EMI 4 CLKID_AHB_USB0 5 CLKID_AHB_USB1 6 CLKID_AHB_DMA0 7 CLKID_AHB_DMA1 8 CLKID_AHB_UART0 9 CLKID_AHB_UART1 10 CLKID_AHB_UART2 11 CLKID_AHB_UART3 12 CLKID_AHB_UART4 13 CLKID_AHB_UART5 14 CLKID_AHB_UART6 15 CLKID_AHB_UART7 16 CLKID_AHB_UART8 17 CLKID_AHB_UART9 18 CLKID_AHB_I2S0 19 CLKID_AHB_I2C0 20 CLKID_AHB_I2C1 21 CLKID_AHB_SSP0 22 CLKID_AHB_IOCONFIG 23 CLKID_AHB_WDT 24 CLKID_AHB_CAN0 25 CLKID_AHB_CAN1 26 CLKID_AHB_MPWM 27 CLKID_AHB_SPI0 28 CLKID_AHB_SPI1 29 CLKID_AHB_QEI 30 CLKID_AHB_QUADSPI0 31 CLKID_AHB_CAMIF 32 CLKID_AHB_LCDIF 33 CLKID_AHB_TIMER0 34 CLKID_AHB_TIMER1 35 CLKID_AHB_TIMER2 36 CLKID_AHB_TIMER3 37 CLKID_AHB_IRQ 38 CLKID_AHB_RTC 39 CLKID_AHB_NAND 40 CLKID_AHB_ADC0 41 CLKID_AHB_LED 42 CLKID_AHB_DAC0 43 CLKID_AHB_LCD 44 CLKID_AHB_I2S1 45 CLKID_AHB_MAC1 46 CLKID_SYS_CPU 47 CLKID_SYS_AHB 48 CLKID_SYS_I2S0M 49 CLKID_SYS_I2S0S 50 CLKID_SYS_I2S1M 51 CLKID_SYS_I2S1S 52 CLKID_SYS_UART0 53 CLKID_SYS_UART1 54 CLKID_SYS_UART2 55 CLKID_SYS_UART3 56 CLKID_SYS_UART4 56 CLKID_SYS_UART5 57 CLKID_SYS_UART6 58 CLKID_SYS_UART7 59 CLKID_SYS_UART8 60 CLKID_SYS_UART9 61 CLKID_SYS_SPI0 62 CLKID_SYS_SPI1 63 CLKID_SYS_QUADSPI 64 CLKID_SYS_SSP0 65 CLKID_SYS_NAND 66 CLKID_SYS_TRACE 67 CLKID_SYS_CAMM 68 CLKID_SYS_WDT 69 CLKID_SYS_CLKOUT 70 CLKID_SYS_MAC 71 CLKID_SYS_LCD 72 CLKID_SYS_ADCANA 73 Example of clock consumer with _SYS_ and _AHB_ sinks. uart4: serial@80010000 { compatible = "alphascale,asm9260-uart"; reg = <0x80010000 0x4000>; clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>; interrupts = <19>; }; Clock consumer with only one, _AHB_ sink. timer0: timer@80088000 { compatible = "alphascale,asm9260-timer"; reg = <0x80088000 0x4000>; clocks = <&acc CLKID_AHB_TIMER0>; interrupts = <29>; }; |