Based on kernel version 6.10
. Page generated on 2024-07-16 08:59 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mobileye EyeQ5 clock controller description: The EyeQ5 clock controller handles 10 read-only PLLs derived from the main crystal clock. It also exposes one divider clock, a child of one of the PLLs. Its registers live in a shared region called OLB. maintainers: - Grégory Clement <gregory.clement@bootlin.com> - Théo Lebrun <theo.lebrun@bootlin.com> - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> properties: compatible: const: mobileye,eyeq5-clk reg: maxItems: 2 reg-names: items: - const: plls - const: ospi "#clock-cells": const: 1 clocks: maxItems: 1 description: Input parent clock to all PLLs. Expected to be the main crystal. clock-names: items: - const: ref required: - compatible - reg - reg-names - "#clock-cells" - clocks - clock-names additionalProperties: false |