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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek System Clock Controller for MT6795 maintainers: - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> - Chun-Jie Chen <chun-jie.chen@mediatek.com> description: The Mediatek system clock controller provides various clocks and system configuration like reset and bus protection on MT6795. properties: compatible: items: - enum: - mediatek,mt6795-apmixedsys - mediatek,mt6795-infracfg - mediatek,mt6795-pericfg - mediatek,mt6795-topckgen - const: syscon reg: maxItems: 1 '#clock-cells': const: 1 '#reset-cells': const: 1 required: - compatible - reg - '#clock-cells' additionalProperties: false examples: - | soc { #address-cells = <2>; #size-cells = <2>; topckgen: clock-controller@10000000 { compatible = "mediatek,mt6795-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; #clock-cells = <1>; }; }; |