Based on kernel version 7.3. Page generated on 2026-10-19 13:17 EDT.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/sound/mediatek,mtk-btcvsd-snd.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek ALSA BT SCO CVSD/MSBC maintainers: - Luca Leonardo Scorcia <l.scorcia@gmail.com> properties: compatible: const: mediatek,mtk-btcvsd-snd reg: items: - description: PKV region - description: SRAM_BANK2 region interrupts: items: - description: BT-SCO interrupt mediatek,infracfg: $ref: /schemas/types.yaml#/definitions/phandle description: The phandle of the infracfg controller mediatek,offset: $ref: /schemas/types.yaml#/definitions/uint32-array description: Array of register offsets and masks items: - description: infra_misc_offset - description: infra_conn_bt_cvsd_mask - description: cvsd_mcu_read_offset - description: cvsd_mcu_write_offset - description: cvsd_packet_indicator_offset required: - compatible - reg - interrupts - mediatek,infracfg - mediatek,offset additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> mtk-btcvsd-snd@18000000 { compatible = "mediatek,mtk-btcvsd-snd"; reg = <0x18000000 0x1000>, <0x18080000 0x8000>; interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; mediatek,infracfg = <&infrasys>; mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>; }; |