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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Tegra210 ADMAIF description: | ADMAIF is the interface between ADMA and AHUB. Each ADMA channel that sends/receives data to/from AHUB must interface through an ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF Tx channel and ADMA channel receiving data from AHUB pairs with ADMAIF Rx channel. maintainers: - Jon Hunter <jonathanh@nvidia.com> - Sameer Pujar <spujar@nvidia.com> properties: $nodename: pattern: "^admaif@[0-9a-f]*$" compatible: oneOf: - enum: - nvidia,tegra210-admaif - nvidia,tegra186-admaif - items: - enum: - nvidia,tegra234-admaif - nvidia,tegra194-admaif - const: nvidia,tegra186-admaif reg: maxItems: 1 dmas: true dma-names: true ports: $ref: /schemas/graph.yaml#/properties/ports description: | Contains list of ACIF (Audio CIF) port nodes for ADMAIF channels. The number of port nodes depends on the number of ADMAIF channels that SoC may have. These are interfaced with respective ACIF ports in AHUB (Audio Hub). Each port is capable of data transfers in both directions. patternProperties: '^port@[0-9]': $ref: audio-graph-port.yaml# unevaluatedProperties: false if: properties: compatible: contains: const: nvidia,tegra210-admaif then: properties: dmas: description: DMA channel specifiers, equally divided for Tx and Rx. minItems: 1 maxItems: 20 dma-names: items: pattern: "^[rt]x(10|[1-9])$" description: Should be "rx1", "rx2" ... "rx10" for DMA Rx channel Should be "tx1", "tx2" ... "tx10" for DMA Tx channel minItems: 1 maxItems: 20 else: properties: dmas: description: DMA channel specifiers, equally divided for Tx and Rx. minItems: 1 maxItems: 40 dma-names: items: pattern: "^[rt]x(1[0-9]|[1-9]|20)$" description: Should be "rx1", "rx2" ... "rx20" for DMA Rx channel Should be "tx1", "tx2" ... "tx20" for DMA Tx channel minItems: 1 maxItems: 40 required: - compatible - reg - dmas - dma-names additionalProperties: false examples: - | admaif@702d0000 { compatible = "nvidia,tegra210-admaif"; reg = <0x702d0000 0x800>; dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, <&adma 4>, <&adma 4>, <&adma 5>, <&adma 5>, <&adma 6>, <&adma 6>, <&adma 7>, <&adma 7>, <&adma 8>, <&adma 8>, <&adma 9>, <&adma 9>, <&adma 10>, <&adma 10>; dma-names = "rx1", "tx1", "rx2", "tx2", "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", "rx9", "tx9", "rx10", "tx10"; }; ... |