Documentation / devicetree / bindings / sound / amlogic,axg-tdm-formatters.yaml


Based on kernel version 6.10. Page generated on 2024-07-16 09:00 EST.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-formatters.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic Audio AXG TDM formatters

maintainers:
  - Jerome Brunet <jbrunet@baylibre.com>

properties:
  compatible:
    enum:
      - amlogic,g12a-tdmout
      - amlogic,sm1-tdmout
      - amlogic,axg-tdmout
      - amlogic,g12a-tdmin
      - amlogic,sm1-tdmin
      - amlogic,axg-tdmin

  clocks:
    items:
      - description: Peripheral clock
      - description: Bit clock
      - description: Bit clock input multiplexer
      - description: Sample clock
      - description: Sample clock input multiplexer

  clock-names:
    items:
      - const: pclk
      - const: sclk
      - const: sclk_sel
      - const: lrclk
      - const: lrclk_sel

  reg:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names

allOf:
  - $ref: component-common.yaml#

  - if:
      properties:
        compatible:
          contains:
            enum:
              - amlogic,g12a-tdmin
              - amlogic,sm1-tdmin
              - amlogic,g12a-tdmout
              - amlogic,sm1-tdmout
    then:
      required:
        - resets

    else:
      properties:
        resets: false

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/axg-audio-clkc.h>
    #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
 
    audio-controller@500 {
        compatible = "amlogic,g12a-tdmout";
        reg = <0x500 0x40>;
        resets = <&clkc_audio AUD_RESET_TDMOUT_A>;
        clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
                 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
                 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
                 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
                 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
        clock-names = "pclk", "sclk", "sclk_sel",
                      "lrclk", "lrclk_sel";
    };