Documentation / devicetree / bindings / sound / fsl,esai.yaml


Based on kernel version 6.11. Page generated on 2024-09-24 08:21 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,esai.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Enhanced Serial Audio Interface (ESAI) Controller

maintainers:
  - Shengjiu Wang <shengjiu.wang@nxp.com>
  - Frank Li <Frank.Li@nxp.com>

description:
  The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
  for serial communication with a variety of serial devices, including industry
  standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
  other DSPs. It has up to six transmitters and four receivers.

properties:
  compatible:
    enum:
      - fsl,imx35-esai
      - fsl,imx6ull-esai
      - fsl,imx8qm-esai
      - fsl,vf610-esai

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    items:
      - description:
          The core clock used to access registers.
      - description:
          The esai baud clock for esai controller used to
          derive HCK, SCK and FS.
      - description:
          The system clock derived from ahb clock used to
          derive HCK, SCK and FS.
      - description:
          The spba clock is required when ESAI is placed as a
          bus slave of the Shared Peripheral Bus and when two
          or more bus masters (CPU, DMA or DSP) try to access
          it. This property is optional depending on the SoC
          design.

  clock-names:
    minItems: 3
    items:
      - const: core
      - const: extal
      - const: fsys
      - const: spba

  dmas:
    minItems: 2
    maxItems: 2

  dma-names:
    items:
      - const: rx
      - const: tx

  fsl,fifo-depth:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 64
    description:
      The number of elements in the transmit and receive
      FIFOs. This number is the maximum allowed value for
      TFCR[TFWM] or RFCR[RFWM].

  fsl,esai-synchronous:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      This is a boolean property. If present, indicating
      that ESAI would work in the synchronous mode, which
      means all the settings for Receiving would be
      duplicated from Transmission related registers.

  big-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      If this property is absent, the native endian mode
      will be in use as default, or the big endian mode
      will be in use for all the device registers.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - dmas
  - dma-names

unevaluatedProperties: false

allOf:
  - $ref: dai-common.yaml#

examples:
  - |
    esai@2024000 {
      compatible = "fsl,imx35-esai";
      reg = <0x02024000 0x4000>;
      interrupts = <0 51 0x04>;
      clocks = <&clks 208>, <&clks 118>, <&clks 208>;
      clock-names = "core", "extal", "fsys";
      dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
      dma-names = "rx", "tx";
      fsl,fifo-depth = <128>;
      fsl,esai-synchronous;
      big-endian;
    };