Based on kernel version 7.3. Page generated on 2026-10-19 13:17 EDT.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6858-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek MT6858 Pin Controller maintainers: - Nikolai Burov <nikolai.burov@jolla.com> description: The MediaTek's MT6858 Pin controller is used to control SoC pins. properties: compatible: const: mediatek,mt6858-pinctrl reg: items: - description: gpio base - description: lm group IO - description: rb group IO - description: bm2 group IO - description: bm group IO - description: bm1 group IO - description: lt group IO - description: lt1 group IO - description: rt group IO - description: rt1 group IO - description: eint south group IO - description: eint west group IO - description: eint east group IO - description: eint center group IO reg-names: items: - const: base - const: lm - const: rb - const: bm2 - const: bm - const: bm1 - const: lt - const: lt1 - const: rt - const: rt1 - const: eint0 - const: eint1 - const: eint2 - const: eint3 interrupts: maxItems: 1 interrupt-controller: true '#interrupt-cells': const: 2 gpio-controller: true '#gpio-cells': const: 2 gpio-ranges: maxItems: 1 gpio-line-names: true # PIN CONFIGURATION NODES patternProperties: '-pins$': type: object additionalProperties: false patternProperties: '^pins': type: object $ref: /schemas/pinctrl/pincfg-node.yaml additionalProperties: false description: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer configuration, pullups, drive strength, input enable/disable and input schmitt. properties: pinmux: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are defined as macros in arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h for this SoC. drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] bias-pull-down: oneOf: - type: boolean description: normal pull down. - enum: [100, 101, 102, 103] description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_ defines in dt-bindings/pinctrl/mt65xx.h. - enum: [200, 201, 202, 203] description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines in dt-bindings/pinctrl/mt65xx.h. bias-pull-up: oneOf: - type: boolean description: normal pull up. - enum: [100, 101, 102, 103] description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_ defines in dt-bindings/pinctrl/mt65xx.h. - enum: [200, 201, 202, 203] description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines in dt-bindings/pinctrl/mt65xx.h. bias-disable: true output-high: true output-low: true input-enable: true input-disable: true input-schmitt-enable: true input-schmitt-disable: true required: - pinmux required: - compatible - reg - interrupts - interrupt-controller - '#interrupt-cells' - gpio-controller - '#gpio-cells' - gpio-ranges additionalProperties: false examples: - | #include <dt-bindings/pinctrl/mt65xx.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #define PINMUX_GPIO149__FUNC_SCL5 (MTK_PIN_NO(149) | 1) #define PINMUX_GPIO150__FUNC_SDA5 (MTK_PIN_NO(150) | 1) pio: pinctrl@10005000 { compatible = "mediatek,mt6858-pinctrl"; reg = <0x10005000 0x1000>, <0x11b20000 0x1000>, <0x11c10000 0x1000>, <0x11d10000 0x1000>, <0x11d30000 0x1000>, <0x11d40000 0x1000>, <0x11e20000 0x1000>, <0x11e30000 0x1000>, <0x11ed0000 0x1000>, <0x11ee0000 0x1000>, <0x11b00000 0x1000>, <0x11e60000 0x1000>, <0x11e80000 0x1000>, <0x1c01e000 0x1000>; reg-names = "base", "lm", "rb", "bm2", "bm", "bm1", "lt", "lt1", "rt", "rt1", "eint0", "eint1", "eint2", "eint3"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pio 0 0 197>; interrupt-controller; interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; #interrupt-cells = <2>; i2c5-pins { pins { pinmux = <PINMUX_GPIO149__FUNC_SCL5>, <PINMUX_GPIO150__FUNC_SDA5>; bias-disable; }; }; }; |