Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. SM6125 TLMM block maintainers: - Martin Botka <martin.botka@somainline.org> description: Top Level Mode Multiplexer pin controller in Qualcomm SM6125 SoC. allOf: - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# properties: compatible: const: qcom,sm6125-tlmm reg: maxItems: 3 reg-names: items: - const: west - const: south - const: east interrupts: maxItems: 1 gpio-reserved-ranges: true patternProperties: "-state$": oneOf: - $ref: "#/$defs/qcom-sm6125-tlmm-state" - patternProperties: "-pins$": $ref: "#/$defs/qcom-sm6125-tlmm-state" additionalProperties: false $defs: qcom-sm6125-tlmm-state: type: object description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state unevaluatedProperties: false properties: pins: description: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 function: description: Specify the alternative function to be configured for the specified pins. enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb, audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk, dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte, nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable, qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04, qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx, swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ] required: - pins required: - compatible - reg - reg-names unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> pinctrl@500000 { compatible = "qcom,sm6125-tlmm"; reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>; reg-names = "west", "south", "east"; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; gpio-ranges = <&tlmm 0 0 134>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; sdc2-off-state { clk-pins { pins = "sdc2_clk"; drive-strength = <2>; bias-disable; }; cmd-pins { pins = "sdc2_cmd"; drive-strength = <2>; bias-pull-up; }; data-pins { pins = "sdc2_data"; drive-strength = <2>; bias-pull-up; }; }; }; |