Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Nuvoton NPCM845 Pin Controller and GPIO maintainers: - Tomer Maimon <tmaimon77@gmail.com> description: The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through the multiplexing block, Each pin supports GPIO functionality (GPIOx) and multiple functions that directly connect the pin to different hardware blocks. properties: compatible: const: nuvoton,npcm845-pinctrl ranges: maxItems: 1 '#address-cells': const: 1 '#size-cells': const: 1 nuvoton,sysgcr: $ref: /schemas/types.yaml#/definitions/phandle description: a phandle to access GCR registers. patternProperties: '^gpio@': type: object additionalProperties: false description: Eight GPIO banks that each contain 32 GPIOs. properties: gpio-controller: true '#gpio-cells': const: 2 reg: maxItems: 1 interrupts: maxItems: 1 gpio-ranges: maxItems: 1 required: - gpio-controller - '#gpio-cells' - reg - interrupts - gpio-ranges '-mux$': $ref: pinmux-node.yaml# properties: groups: description: One or more groups of pins to mux to a certain function items: enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b, smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk, scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ] function: description: The function that a group of pins is muxed to enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b, smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk, scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ] dependencies: groups: [ function ] function: [ groups ] additionalProperties: false '^pin': $ref: pincfg-node.yaml# properties: pins: description: A list of pins to configure in certain ways, such as enabling debouncing items: pattern: '^GPIO([0-9]|[0-9][0-9]|1[0-9][0-9]|2[0-4][0-9]|25[0-6])' bias-disable: true bias-pull-up: true bias-pull-down: true input-enable: true output-low: true output-high: true drive-push-pull: true drive-open-drain: true input-debounce: description: Debouncing periods in microseconds, one period per interrupt bank found in the controller minItems: 1 maxItems: 4 slew-rate: description: | 0: Low rate 1: High rate enum: [0, 1] drive-strength: enum: [ 0, 1, 2, 4, 8, 12 ] additionalProperties: false allOf: - $ref: pinctrl.yaml# required: - compatible - ranges - '#address-cells' - '#size-cells' - nuvoton,sysgcr additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> soc { #address-cells = <2>; #size-cells = <2>; pinctrl: pinctrl@f0010000 { compatible = "nuvoton,npcm845-pinctrl"; ranges = <0x0 0x0 0xf0010000 0x8000>; #address-cells = <1>; #size-cells = <1>; nuvoton,sysgcr = <&gcr>; gpio0: gpio@0 { gpio-controller; #gpio-cells = <2>; reg = <0x0 0xb0>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; gpio-ranges = <&pinctrl 0 0 32>; }; fanin0_pin: fanin0-mux { groups = "fanin0"; function = "fanin0"; }; pin34_slew: pin34-slew { pins = "GPIO34/I3C4_SDA"; bias-disable; }; }; }; |