Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) # Copyright (C) STMicroelectronics 2019. %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: STM32 GPIO and Pin Mux/Config controller maintainers: - Alexandre TORGUE <alexandre.torgue@foss.st.com> description: | STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware controller. It controls the input/output settings on the available pins and also provides ability to multiplex and configure the output of various on-chip controllers onto these pads. properties: compatible: enum: - st,stm32f429-pinctrl - st,stm32f469-pinctrl - st,stm32f746-pinctrl - st,stm32f769-pinctrl - st,stm32h743-pinctrl - st,stm32mp135-pinctrl - st,stm32mp157-pinctrl - st,stm32mp157-z-pinctrl - st,stm32mp257-pinctrl - st,stm32mp257-z-pinctrl '#address-cells': const: 1 '#size-cells': const: 1 ranges: true pins-are-numbered: $ref: /schemas/types.yaml#/definitions/flag deprecated: true hwlocks: true interrupts: maxItems: 1 st,syscfg: description: Phandle+args to the syscon node which includes IRQ mux selection. $ref: /schemas/types.yaml#/definitions/phandle-array items: - minItems: 2 items: - description: syscon node which includes IRQ mux selection - description: The offset of the IRQ mux selection register - description: The field mask of IRQ mux, needed if different of 0xf st,package: description: Indicates the SOC package used. More details in include/dt-bindings/pinctrl/stm32-pinfunc.h $ref: /schemas/types.yaml#/definitions/uint32 enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800] patternProperties: '^gpio@[0-9a-f]*$': type: object additionalProperties: false properties: gpio-controller: true '#gpio-cells': const: 2 interrupt-controller: true '#interrupt-cells': const: 2 reg: maxItems: 1 clocks: maxItems: 1 resets: maxItems: 1 gpio-line-names: true gpio-ranges: minItems: 1 maxItems: 16 ngpios: description: Number of available gpios in a bank. minimum: 1 maximum: 16 st,bank-name: description: Should be a name string for this bank as specified in the datasheet. $ref: /schemas/types.yaml#/definitions/string enum: - GPIOA - GPIOB - GPIOC - GPIOD - GPIOE - GPIOF - GPIOG - GPIOH - GPIOI - GPIOJ - GPIOK - GPIOZ st,bank-ioport: description: Should correspond to the EXTI IOport selection (EXTI line used to select GPIOs as interrupts). $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 11 patternProperties: "^(.+-hog(-[0-9]+)?)$": type: object required: - gpio-hog required: - gpio-controller - '#gpio-cells' - reg - clocks - st,bank-name '-[0-9]*$': type: object additionalProperties: false patternProperties: '^pins': type: object additionalProperties: false description: | A pinctrl node should contain at least one subnode representing the pinctrl group available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer configuration, pullups, drive, output high/low and output speed. properties: pinmux: $ref: /schemas/types.yaml#/definitions/uint32-array description: | Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly. These defines are calculated as: ((port * 16 + line) << 8) | function With: - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) - function: The function number, can be: * 0 : GPIO * 1 : Alternate Function 0 * 2 : Alternate Function 1 * 3 : Alternate Function 2 * ... * 16 : Alternate Function 15 * 17 : Analog To simplify the usage, macro is available to generate "pinmux" field. This macro is available here: - include/dt-bindings/pinctrl/stm32-pinfunc.h Some examples of using macro: /* GPIO A9 set as alernate function 2 */ ... { pinmux = <STM32_PINMUX('A', 9, AF2)>; }; /* GPIO A9 set as GPIO */ ... { pinmux = <STM32_PINMUX('A', 9, GPIO)>; }; /* GPIO A9 set as analog */ ... { pinmux = <STM32_PINMUX('A', 9, ANALOG)>; }; bias-disable: type: boolean bias-pull-down: type: boolean bias-pull-up: type: boolean drive-push-pull: type: boolean drive-open-drain: type: boolean output-low: type: boolean output-high: type: boolean slew-rate: description: | 0: Low speed 1: Medium speed 2: Fast speed 3: High speed $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] required: - pinmux allOf: - $ref: pinctrl.yaml# required: - compatible - '#address-cells' - '#size-cells' - ranges additionalProperties: false examples: - | #include <dt-bindings/pinctrl/stm32-pinfunc.h> #include <dt-bindings/mfd/stm32f4-rcc.h> //Example 1 pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f429-pinctrl"; ranges = <0 0x40020000 0x3000>; gpioa: gpio@0 { gpio-controller; #gpio-cells = <2>; reg = <0x0 0x400>; resets = <&reset_ahb1 0>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; st,bank-name = "GPIOA"; }; }; //Example 2 (using gpio-ranges) pinctrl@50020000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32f429-pinctrl"; ranges = <0 0x50020000 0x3000>; gpiob: gpio@1000 { gpio-controller; #gpio-cells = <2>; reg = <0x1000 0x400>; resets = <&reset_ahb1 0>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; st,bank-name = "GPIOB"; gpio-ranges = <&pinctrl 0 0 16>; }; gpioc: gpio@2000 { gpio-controller; #gpio-cells = <2>; reg = <0x2000 0x400>; resets = <&reset_ahb1 0>; clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; st,bank-name = "GPIOC"; ngpios = <5>; gpio-ranges = <&pinctrl 0 16 3>, <&pinctrl 14 30 2>; }; }; //Example 3 pin groups pinctrl { usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('A', 9, AF7)>; bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { pinmux = <STM32_PINMUX('A', 10, AF7)>; bias-disable; }; }; }; usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; }; ... |