Based on kernel version 6.13
. Page generated on 2025-01-21 08:20 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 | Broadcom NSP (Northstar plus) IOMUX Controller The NSP IOMUX controller supports group based mux configuration. In addition, certain pins can be muxed to GPIO function individually. Required properties: - compatible: Must be "brcm,nsp-pinmux" - reg: Should contain the register physical address and length for each of GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers Properties in subnodes: - function: The mux function to select - groups: The list of groups to select with a given function For more details, refer to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt For example: pinmux: pinmux@1803f1c0 { compatible = "brcm,nsp-pinmux"; reg = <0x1803f1c0 0x04>, <0x18030028 0x04>, <0x1803f408 0x04>; pinctrl-names = "default"; pinctrl-0 = <&pwm>, <&gpio_b>, <&nand_sel>; pwm: pwm { function = "pwm"; groups = "pwm0_grp", "pwm1_grp"; }; gpio_b: gpio_b { function = "gpio_b"; groups = "gpio_b_0_grp", "gpio_b_1_grp"; }; nand_sel: nand_sel { function = "nand"; groups = "nand_grp"; }; }; List of supported functions and groups in Northstar Plus: "spi": "spi_grp" "i2c": "i2c_grp" "mdio": "mdio_grp" "pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp" "gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp" "uart1": "uart1_grp" "uart2": "uart2_grp" "synce": "synce_grp" "sata_led_grps": "sata0_led_grp", "sata1_led_grp" "xtal_out": "xtal_out_grp" "sdio": "sdio_pwr_grp", "sdio_1p8v_grp" "switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp" "nand": "nand_grp" "emmc": "emmc_grp" |