Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. SDX55 TLMM block maintainers: - Vinod Koul <vkoul@kernel.org> description: Top Level Mode Multiplexer pin controller in Qualcomm SDX55 SoC. properties: compatible: const: qcom,sdx55-pinctrl reg: description: Specifies the base address and size of the TLMM register space maxItems: 1 interrupts: maxItems: 1 gpio-reserved-ranges: maxItems: 1 patternProperties: "-state$": oneOf: - $ref: "#/$defs/qcom-sdx55-tlmm-state" - patternProperties: "-pins$": $ref: "#/$defs/qcom-sdx55-tlmm-state" additionalProperties: false $defs: qcom-sdx55-tlmm-state: type: object description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state unevaluatedProperties: false properties: pins: description: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 function: description: Specify the alternative function to be configured for the specified pins. Functions are only valid for gpio pins. enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1, emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3, gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update, mgpi_clk, m_voc, native_char, native_char0, native_char1, native_char2, native_char3, native_tsens, native_tsense, nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref, pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2, qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7, qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12, qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17, qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22, qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27, qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en, qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss, spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, usb2phy_ac, vsense_trigger ] required: - pins allOf: - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# required: - compatible - reg unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> tlmm: pinctrl@1f00000 { compatible = "qcom,sdx55-pinctrl"; reg = <0x0f100000 0x300000>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&tlmm 0 0 108>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; serial-state { pins = "gpio8", "gpio9"; function = "blsp_uart3"; drive-strength = <8>; bias-disable; }; }; ... |