Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: StarFive JH7110 SYS Pin Controller description: | Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63 can be multiplexed and have configurable bias, drive strength, schmitt trigger etc. Some peripherals have their I/O go through the 64 "GPIOs". This also includes a number of other UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64 GPIOs such that any GPIO can be set up to be controlled by any of the peripherals. maintainers: - Jianlong Huang <jianlong.huang@starfivetech.com> properties: compatible: const: starfive,jh7110-sys-pinctrl reg: maxItems: 1 clocks: maxItems: 1 resets: maxItems: 1 interrupts: maxItems: 1 interrupt-controller: true '#interrupt-cells': const: 2 gpio-controller: true '#gpio-cells': const: 2 patternProperties: '-[0-9]+$': type: object additionalProperties: false patternProperties: '-pins$': type: object description: | A pinctrl node should contain at least one subnode representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer configuration, bias, input enable/disable, input schmitt trigger enable/disable, slew-rate and drive strength. allOf: - $ref: /schemas/pinctrl/pincfg-node.yaml - $ref: /schemas/pinctrl/pinmux-node.yaml additionalProperties: false properties: pinmux: description: | The list of GPIOs and their mux settings that properties in the node apply to. This should be set using the GPIOMUX or PINMUX macros. bias-disable: true bias-pull-up: type: boolean bias-pull-down: type: boolean drive-strength: enum: [ 2, 4, 8, 12 ] input-enable: true input-disable: true input-schmitt-enable: true input-schmitt-disable: true slew-rate: maximum: 1 required: - compatible - reg - clocks - interrupts - interrupt-controller - '#interrupt-cells' - gpio-controller - '#gpio-cells' additionalProperties: false examples: - | pinctrl@13040000 { compatible = "starfive,jh7110-sys-pinctrl"; reg = <0x13040000 0x10000>; clocks = <&syscrg 112>; resets = <&syscrg 2>; interrupts = <86>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; uart0-0 { tx-pins { pinmux = <0xff140005>; bias-disable; drive-strength = <12>; input-disable; input-schmitt-disable; slew-rate = <0>; }; rx-pins { pinmux = <0x0E000406>; bias-pull-up; drive-strength = <2>; input-enable; input-schmitt-enable; slew-rate = <0>; }; }; }; ... |