Based on kernel version 6.10
. Page generated on 2024-07-16 09:00 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Layerscape PCIe Root Complex(RC) controller maintainers: - Frank Li <Frank.Li@nxp.com> description: This PCIe RC controller is based on the Synopsys DesignWare PCIe IP This controller derives its clocks from the Reset Configuration Word (RCW) which is used to describe the PLL settings at the time of chip-reset. Also as per the available Reference Manuals, there is no specific 'version' register available in the Freescale PCIe controller register set, which can allow determining the underlying DesignWare PCIe controller version information. properties: compatible: enum: - fsl,ls1021a-pcie - fsl,ls2080a-pcie - fsl,ls2085a-pcie - fsl,ls2088a-pcie - fsl,ls1088a-pcie - fsl,ls1046a-pcie - fsl,ls1043a-pcie - fsl,ls1012a-pcie - fsl,ls1028a-pcie - fsl,lx2160a-pcie reg: maxItems: 2 reg-names: items: - const: regs - const: config fsl,pcie-scfg: $ref: /schemas/types.yaml#/definitions/phandle description: A phandle to the SCFG device node. The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers. big-endian: $ref: /schemas/types.yaml#/definitions/flag description: If the PEX_LUT and PF register block is in big-endian, specify this property. dma-coherent: true msi-parent: true iommu-map: true interrupts: minItems: 1 maxItems: 2 interrupt-names: minItems: 1 maxItems: 2 required: - compatible - reg - reg-names - "#address-cells" - "#size-cells" - device_type - bus-range - ranges - interrupts - interrupt-names - "#interrupt-cells" - interrupt-map-mask - interrupt-map allOf: - $ref: /schemas/pci/pci-bus.yaml# - if: properties: compatible: enum: - fsl,ls1028a-pcie - fsl,ls1046a-pcie - fsl,ls1043a-pcie - fsl,ls1012a-pcie then: properties: interrupts: maxItems: 2 interrupt-names: items: - const: pme - const: aer - if: properties: compatible: enum: - fsl,ls2080a-pcie - fsl,ls2085a-pcie - fsl,ls2088a-pcie then: properties: interrupts: maxItems: 1 interrupt-names: items: - const: intr - if: properties: compatible: enum: - fsl,ls1088a-pcie then: properties: interrupts: maxItems: 1 interrupt-names: items: - const: aer unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> soc { #address-cells = <2>; #size-cells = <2>; pcie@3400000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; dma-coherent; device_type = "pci"; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&its>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ }; }; ... |