Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung SoC series PCIe Host Controller maintainers: - Marek Szyprowski <m.szyprowski@samsung.com> - Jaehoon Chung <jh80.chung@samsung.com> description: |+ Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# properties: compatible: const: samsung,exynos5433-pcie reg: items: - description: Data Bus Interface (DBI) registers. - description: External Local Bus interface (ELBI) registers. - description: PCIe configuration space region. reg-names: items: - const: dbi - const: elbi - const: config interrupts: maxItems: 1 clocks: items: - description: PCIe bridge clock - description: PCIe bus clock clock-names: items: - const: pcie - const: pcie_bus phys: maxItems: 1 vdd10-supply: description: Phandle to a regulator that provides 1.0V power to the PCIe block. vdd18-supply: description: Phandle to a regulator that provides 1.8V power to the PCIe block. num-lanes: const: 1 num-viewport: const: 3 required: - reg - reg-names - interrupts - "#address-cells" - "#size-cells" - "#interrupt-cells" - interrupt-map - interrupt-map-mask - ranges - bus-range - device_type - num-lanes - num-viewport - clocks - clock-names - phys - vdd10-supply - vdd18-supply unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/exynos5433.h> pcie: pcie@15700000 { compatible = "samsung,exynos5433-pcie"; reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>; reg-names = "dbi", "elbi", "config"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; clock-names = "pcie", "pcie_bus"; phys = <&pcie_phy>; pinctrl-0 = <&pcie_bus &pcie_wlanen>; pinctrl-names = "default"; num-lanes = <1>; num-viewport = <3>; bus-range = <0x00 0xff>; ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; vdd10-supply = <&ldo6_reg>; vdd18-supply = <&ldo7_reg>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; }; ... |