Documentation / devicetree / bindings / pci / qcom,pcie-sc8180x.yaml


Based on kernel version 6.10. Page generated on 2024-07-16 09:00 EST.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC8180x PCI Express Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

description:
  Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
  DesignWare PCIe IP.

properties:
  compatible:
    const: qcom,pcie-sc8180x

  reg:
    minItems: 5
    maxItems: 6

  reg-names:
    minItems: 5
    items:
      - const: parf # Qualcomm specific registers
      - const: dbi # DesignWare PCIe registers
      - const: elbi # External local bus interface registers
      - const: atu # ATU address space
      - const: config # PCIe configuration space
      - const: mhi # MHI registers

  clocks:
    minItems: 8
    maxItems: 8

  clock-names:
    items:
      - const: pipe # PIPE clock
      - const: aux # Auxiliary clock
      - const: cfg # Configuration clock
      - const: bus_master # Master AXI clock
      - const: bus_slave # Slave AXI clock
      - const: slave_q2a # Slave Q2A clock
      - const: ref # REFERENCE clock
      - const: tbu # PCIe TBU clock

  interrupts:
    minItems: 8
    maxItems: 8

  interrupt-names:
    items:
      - const: msi0
      - const: msi1
      - const: msi2
      - const: msi3
      - const: msi4
      - const: msi5
      - const: msi6
      - const: msi7

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: pci

allOf:
  - $ref: qcom,pcie-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
    #include <dt-bindings/interconnect/qcom,sc8180x.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
    soc {
        #address-cells = <2>;
        #size-cells = <2>;
 
        pcie@1c00000 {
            compatible = "qcom,pcie-sc8180x";
            reg = <0 0x01c00000 0 0x3000>,
                  <0 0x60000000 0 0xf1d>,
                  <0 0x60000f20 0 0xa8>,
                  <0 0x60001000 0 0x1000>,
                  <0 0x60100000 0 0x100000>;
            reg-names = "parf",
                        "dbi",
                        "elbi",
                        "atu",
                        "config";
            ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
 
            bus-range = <0x00 0xff>;
            device_type = "pci";
            linux,pci-domain = <0>;
            num-lanes = <2>;
 
            #address-cells = <3>;
            #size-cells = <2>;
 
            assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
            assigned-clock-rates = <19200000>;
 
            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
                     <&gcc GCC_PCIE_0_AUX_CLK>,
                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
                     <&gcc GCC_PCIE_0_CLKREF_CLK>,
                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
            clock-names = "pipe",
                          "aux",
                          "cfg",
                          "bus_master",
                          "bus_slave",
                          "slave_q2a",
                          "ref",
                          "tbu";
 
            dma-coherent;
 
            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "msi0",
                          "msi1",
                          "msi2",
                          "msi3",
                          "msi4",
                          "msi5",
                          "msi6",
                          "msi7";
            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0x7>;
            interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
                            <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
                            <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
                            <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 
            interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
                            <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
            interconnect-names = "pcie-mem", "cpu-pcie";
 
            iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
                        <0x100 &apps_smmu 0x1d81 0x1>;
 
            phys = <&pcie0_phy>;
            phy-names = "pciephy";
 
            power-domains = <&gcc PCIE_0_GDSC>;
 
            resets = <&gcc GCC_PCIE_0_BCR>;
            reset-names = "pci";
        };
    };