Based on kernel version 6.14
. Page generated on 2025-04-02 08:20 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mobiveil AXI PCIe Host Bridge maintainers: - Frank Li <Frank Li@nxp.com> description: Mobiveil's GPEX 4.0 is a PCIe Gen4 host bridge IP. This configurable IP has up to 8 outbound and inbound windows for address translation. NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0. properties: compatible: enum: - fsl,lx2160a-pcie - mbvl,gpex40-pcie reg: items: - description: PCIe controller registers - description: Bridge config registers - description: GPIO registers to control slot power - description: MSI registers minItems: 2 reg-names: items: - const: csr_axi_slave - const: config_axi_slave - const: gpio_slave - const: apb_csr minItems: 2 apio-wins: $ref: /schemas/types.yaml#/definitions/uint32 description: | number of requested APIO outbound windows 1. Config window 2. Memory window default: 2 maximum: 256 ppio-wins: $ref: /schemas/types.yaml#/definitions/uint32 description: number of requested PPIO inbound windows default: 1 maximum: 256 interrupt-controller: true "#interrupt-cells": const: 1 interrupts: minItems: 1 maxItems: 3 interrupt-names: minItems: 1 maxItems: 3 dma-coherent: true msi-parent: true required: - compatible - reg - reg-names allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# - if: properties: compatible: enum: - fsl,lx2160a-pcie then: properties: reg: maxItems: 2 reg-names: maxItems: 2 interrupts: minItems: 3 interrupt-names: items: - const: aer - const: pme - const: intr else: properties: dma-coherent: false msi-parent: false interrupts: maxItems: 1 interrupt-names: false unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> pcie@b0000000 { compatible = "mbvl,gpex40-pcie"; reg = <0xb0000000 0x00010000>, <0xa0000000 0x00001000>, <0xff000000 0x00200000>, <0xb0010000 0x00001000>; reg-names = "csr_axi_slave", "config_axi_slave", "gpio_slave", "apb_csr"; ranges = <0x83000000 0 0x00000000 0xa8000000 0 0x8000000>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; apio-wins = <2>; ppio-wins = <1>; bus-range = <0x00 0xff>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 0 &pci_express 0>, <0 0 0 1 &pci_express 1>, <0 0 0 2 &pci_express 2>, <0 0 0 3 &pci_express 3>; }; - | #include <dt-bindings/interrupt-controller/arm-gic.h> soc { #address-cells = <2>; #size-cells = <2>; pcie@3400000 { compatible = "fsl,lx2160a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ interrupt-names = "aer", "pme", "intr"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; apio-wins = <8>; ppio-wins = <8>; dma-coherent; bus-range = <0x00 0xff>; msi-parent = <&its>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; }; }; |