Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx NWL PCIe Root Port Bridge maintainers: - Thippeswamy Havalige <thippeswamy.havalige@amd.com> allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# - $ref: /schemas/interrupt-controller/msi-controller.yaml# properties: compatible: const: xlnx,nwl-pcie-2.11 reg: items: - description: PCIe bridge registers location. - description: PCIe Controller registers location. - description: PCIe Configuration space region. reg-names: items: - const: breg - const: pcireg - const: cfg interrupts: items: - description: interrupt asserted when miscellaneous interrupt is received - description: unused interrupt(dummy) - description: interrupt asserted when a legacy interrupt is received - description: msi1 interrupt asserted when an MSI is received - description: msi0 interrupt asserted when an MSI is received interrupt-names: items: - const: misc - const: dummy - const: intx - const: msi1 - const: msi0 interrupt-map-mask: items: - const: 0 - const: 0 - const: 0 - const: 7 "#interrupt-cells": const: 1 msi-parent: description: MSI controller the device is capable of using. interrupt-map: maxItems: 4 power-domains: maxItems: 1 iommus: maxItems: 1 dma-coherent: description: optional, only needed if DMA operations are coherent. clocks: maxItems: 1 description: optional, input clock specifier. legacy-interrupt-controller: description: Interrupt controller node for handling legacy PCI interrupts. type: object properties: "#address-cells": const: 0 "#interrupt-cells": const: 1 interrupt-controller: true required: - "#address-cells" - "#interrupt-cells" - interrupt-controller additionalProperties: false required: - compatible - reg - reg-names - interrupts - "#interrupt-cells" - interrupt-map - interrupt-map-mask - msi-controller - power-domains unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> soc { #address-cells = <2>; #size-cells = <2>; nwl_pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; msi-parent = <&nwl_pcie>; power-domains = <&zynqmp_firmware PD_PCIE>; iommus = <&smmu 0x4d0>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; }; |