Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas AHB to PCI bridge maintainers: - Marek Vasut <marek.vasut+renesas@gmail.com> - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> description: | This is the bridge used internally to connect the USB controllers to the AHB. There is one bridge instance per USB port connected to the internal OHCI and EHCI controllers. properties: compatible: oneOf: - items: - enum: - renesas,pci-r8a7742 # RZ/G1H - renesas,pci-r8a7743 # RZ/G1M - renesas,pci-r8a7744 # RZ/G1N - renesas,pci-r8a7745 # RZ/G1E - renesas,pci-r8a7790 # R-Car H2 - renesas,pci-r8a7791 # R-Car M2-W - renesas,pci-r8a7793 # R-Car M2-N - renesas,pci-r8a7794 # R-Car E2 - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 - items: - enum: - renesas,pci-r9a06g032 # RZ/N1D - const: renesas,pci-rzn1 # RZ/N1 reg: items: - description: Operational registers for the OHCI/EHCI controllers. - description: Bridge configuration and control registers. interrupts: maxItems: 1 clocks: true clock-names: true resets: maxItems: 1 power-domains: maxItems: 1 bus-range: description: | The PCI bus number range; as this is a single bus, the range should be specified as the same value twice. dma-ranges: description: | A single range for the inbound memory region. If not supplied, defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the allowed combinations of address and size. maxItems: 1 patternProperties: '^usb@[0-1],0$': type: object description: This a USB controller PCI device properties: reg: description: Identify the correct bus, device and function number in the form <bdf 0 0 0 0>. items: minItems: 5 maxItems: 5 phys: description: Reference to the USB phy maxItems: 1 phy-names: maxItems: 1 required: - reg - phys - phy-names unevaluatedProperties: false required: - compatible - reg - interrupts - interrupt-map - interrupt-map-mask - clocks - power-domains - bus-range - "#address-cells" - "#size-cells" - "#interrupt-cells" allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# - if: properties: compatible: contains: enum: - renesas,pci-rzn1 then: properties: clocks: items: - description: Internal bus clock (AHB) for HOST - description: Internal bus clock (AHB) Power Management - description: PCI clock for USB subsystem clock-names: items: - const: hclkh - const: hclkpm - const: pciclk required: - clock-names else: properties: clocks: items: - description: Device clock clock-names: items: - const: pclk required: - resets unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/r8a7790-cpg-mssr.h> #include <dt-bindings/power/r8a7790-sysc.h> pci@ee090000 { compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; device_type = "pci"; reg = <0xee090000 0xc00>, <0xee080000 0x1100>; clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; resets = <&cpg 703>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; bus-range = <0 0>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>; dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>; interrupt-map-mask = <0xf800 0 0 0x7>; interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; usb@1,0 { reg = <0x800 0 0 0 0>; phys = <&usb0 0>; phy-names = "usb"; }; usb@2,0 { reg = <0x1000 0 0 0 0>; phys = <&usb0 0>; phy-names = "usb"; }; }; |