Documentation / devicetree / bindings / pci / ti,am65-pci-ep.yaml


Based on kernel version 6.10. Page generated on 2024-07-16 09:00 EST.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI AM65 PCI Endpoint

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>

allOf:
  - $ref: pci-ep.yaml#

properties:
  compatible:
    enum:
      - ti,am654-pcie-ep

  reg:
    maxItems: 4

  reg-names:
    items:
      - const: app
      - const: dbics
      - const: addr_space
      - const: atu

  power-domains:
    maxItems: 1

  ti,syscon-pcie-mode:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the SYSCON entry
          - description: pcie_ctrl register offset within SYSCON
    description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.

  interrupts:
    minItems: 1

  dma-coherent: true

required:
  - compatible
  - reg
  - reg-names
  - max-link-speed
  - power-domains
  - ti,syscon-pcie-mode
  - dma-coherent

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/soc/ti,sci_pm_domain.h>
 
    pcie0_ep: pcie-ep@5500000 {
        compatible = "ti,am654-pcie-ep";
        reg =  <0x5500000 0x1000>,
               <0x5501000 0x1000>,
               <0x10000000 0x8000000>,
               <0x5506000 0x1000>;
        reg-names = "app", "dbics", "addr_space", "atu";
        power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
        ti,syscon-pcie-mode = <&scm_conf 0x4060>;
        max-link-speed = <2>;
        dma-coherent;
        interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
    };