Documentation / devicetree / bindings / pci / qcom,pcie-sm8150.yaml


Based on kernel version 6.11. Page generated on 2024-09-24 08:21 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8150 PCI Express Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

description:
  Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
  DesignWare PCIe IP.

properties:
  compatible:
    const: qcom,pcie-sm8150

  reg:
    minItems: 5
    maxItems: 6

  reg-names:
    minItems: 5
    items:
      - const: parf # Qualcomm specific registers
      - const: dbi # DesignWare PCIe registers
      - const: elbi # External local bus interface registers
      - const: atu # ATU address space
      - const: config # PCIe configuration space
      - const: mhi # MHI registers

  clocks:
    minItems: 8
    maxItems: 8

  clock-names:
    items:
      - const: pipe # PIPE clock
      - const: aux # Auxiliary clock
      - const: cfg # Configuration clock
      - const: bus_master # Master AXI clock
      - const: bus_slave # Slave AXI clock
      - const: slave_q2a # Slave Q2A clock
      - const: tbu # PCIe TBU clock
      - const: ref # REFERENCE clock

  interrupts:
    minItems: 8
    maxItems: 8

  interrupt-names:
    items:
      - const: msi0
      - const: msi1
      - const: msi2
      - const: msi3
      - const: msi4
      - const: msi5
      - const: msi6
      - const: msi7

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: pci

allOf:
  - $ref: qcom,pcie-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interconnect/qcom,sm8150.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
    soc {
        #address-cells = <2>;
        #size-cells = <2>;
        pcie@1c00000 {
            compatible = "qcom,pcie-sm8150";
            reg = <0 0x01c00000 0 0x3000>,
                  <0 0x60000000 0 0xf1d>,
                  <0 0x60000f20 0 0xa8>,
                  <0 0x60001000 0 0x1000>,
                  <0 0x60100000 0 0x100000>;
            reg-names = "parf", "dbi", "elbi", "atu", "config";
            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
 
            bus-range = <0x00 0xff>;
            device_type = "pci";
            linux,pci-domain = <0>;
            num-lanes = <1>;
 
            #address-cells = <3>;
            #size-cells = <2>;
 
            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
                     <&gcc GCC_PCIE_0_AUX_CLK>,
                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "pipe",
                          "aux",
                          "cfg",
                          "bus_master",
                          "bus_slave",
                          "slave_q2a",
                          "tbu",
                          "ref";
 
            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "msi0", "msi1", "msi2", "msi3",
                              "msi4", "msi5", "msi6", "msi7";
            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0x7>;
            interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
                            <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
                            <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
                            <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 
            iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
                        <0x100 &apps_smmu 0x1d81 0x1>;
 
            phys = <&pcie0_phy>;
            phy-names = "pciephy";
 
            pinctrl-0 = <&pcie0_default_state>;
            pinctrl-names = "default";
 
            power-domains = <&gcc PCIE_0_GDSC>;
 
            resets = <&gcc GCC_PCIE_0_BCR>;
            reset-names = "pci";
 
            perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
            wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
        };
    };