Based on kernel version 6.11
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm PCIe Endpoint Controller maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> properties: compatible: oneOf: - enum: - qcom,sa8775p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep - items: - const: qcom,sdx65-pcie-ep - const: qcom,sdx55-pcie-ep reg: minItems: 6 items: - description: Qualcomm-specific PARF configuration registers - description: DesignWare PCIe registers - description: External local bus interface registers - description: Address Translation Unit (ATU) registers - description: Memory region used to map remote RC address space - description: BAR memory region - description: DMA register space reg-names: minItems: 6 items: - const: parf - const: dbi - const: elbi - const: atu - const: addr_space - const: mmio - const: dma clocks: minItems: 5 maxItems: 8 clock-names: minItems: 5 maxItems: 8 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two offsets within syscon for Perst enable and Perst separation enable registers $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: Syscon to TCSR system registers - description: Perst enable offset - description: Perst separation enable offset interrupts: minItems: 2 items: - description: PCIe Global interrupt - description: PCIe Doorbell interrupt - description: DMA interrupt interrupt-names: minItems: 2 items: - const: global - const: doorbell - const: dma reset-gpios: description: GPIO used as PERST# input signal maxItems: 1 wake-gpios: description: GPIO used as WAKE# output signal maxItems: 1 interconnects: maxItems: 2 interconnect-names: items: - const: pcie-mem - const: cpu-pcie resets: maxItems: 1 reset-names: const: core power-domains: maxItems: 1 phys: maxItems: 1 phy-names: const: pciephy num-lanes: default: 2 required: - compatible - reg - reg-names - clocks - clock-names - interrupts - interrupt-names - reset-gpios - interconnects - interconnect-names - resets - reset-names - power-domains allOf: - $ref: pci-ep.yaml# - if: properties: compatible: contains: enum: - qcom,sdx55-pcie-ep then: properties: reg: maxItems: 6 reg-names: maxItems: 6 clocks: items: - description: PCIe Auxiliary clock - description: PCIe CFG AHB clock - description: PCIe Master AXI clock - description: PCIe Slave AXI clock - description: PCIe Slave Q2A AXI clock - description: PCIe Sleep clock - description: PCIe Reference clock clock-names: items: - const: aux - const: cfg - const: bus_master - const: bus_slave - const: slave_q2a - const: sleep - const: ref interrupts: maxItems: 2 interrupt-names: maxItems: 2 - if: properties: compatible: contains: enum: - qcom,sm8450-pcie-ep then: properties: reg: maxItems: 6 reg-names: maxItems: 6 clocks: items: - description: PCIe Auxiliary clock - description: PCIe CFG AHB clock - description: PCIe Master AXI clock - description: PCIe Slave AXI clock - description: PCIe Slave Q2A AXI clock - description: PCIe Reference clock - description: PCIe DDRSS SF TBU clock - description: PCIe AGGRE NOC AXI clock clock-names: items: - const: aux - const: cfg - const: bus_master - const: bus_slave - const: slave_q2a - const: ref - const: ddrss_sf_tbu - const: aggre_noc_axi interrupts: maxItems: 2 interrupt-names: maxItems: 2 - if: properties: compatible: contains: enum: - qcom,sa8775p-pcie-ep then: properties: reg: minItems: 7 maxItems: 7 reg-names: minItems: 7 maxItems: 7 clocks: items: - description: PCIe Auxiliary clock - description: PCIe CFG AHB clock - description: PCIe Master AXI clock - description: PCIe Slave AXI clock - description: PCIe Slave Q2A AXI clock clock-names: items: - const: aux - const: cfg - const: bus_master - const: bus_slave - const: slave_q2a interrupts: minItems: 3 maxItems: 3 interrupt-names: minItems: 3 maxItems: 3 unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,gcc-sdx55.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,sdx55.h> #include <dt-bindings/interrupt-controller/arm-gic.h> pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, <0x40000000 0xf1d>, <0x40000f20 0xc8>, <0x40001000 0x1000>, <0x40002000 0x1000>, <0x01c03000 0x3000>; reg-names = "parf", "dbi", "elbi", "atu", "addr_space", "mmio"; clocks = <&gcc GCC_PCIE_AUX_CLK>, <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_MSTR_AXI_CLK>, <&gcc GCC_PCIE_SLV_AXI_CLK>, <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_SLEEP_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "sleep", "ref"; qcom,perst-regs = <&tcsr 0xb258 0xb270>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "global", "doorbell"; interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>, <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>; interconnect-names = "pcie-mem", "cpu-pcie"; reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; phys = <&pcie0_lane>; phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; }; |