Based on kernel version 6.13
. Page generated on 2025-01-21 08:20 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) # Copyright (C) 2015, 2024, Intel Corporation %YAML 1.2 --- $id: http://devicetree.org/schemas/altr,msi-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera PCIe MSI controller maintainers: - Matthew Gerlach <matthew.gerlach@linux.intel.com> properties: compatible: enum: - altr,msi-1.0 reg: items: - description: CSR registers - description: Vectors slave port region reg-names: items: - const: csr - const: vector_slave interrupts: maxItems: 1 msi-controller: true num-vectors: description: number of vectors $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 32 required: - compatible - reg - reg-names - interrupts - msi-controller - num-vectors allOf: - $ref: /schemas/interrupt-controller/msi-controller.yaml# unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> msi@ff200000 { compatible = "altr,msi-1.0"; reg = <0xff200000 0x00000010>, <0xff200010 0x00000080>; reg-names = "csr", "vector_slave"; interrupt-parent = <&hps_0_arm_gic_0>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; msi-controller; num-vectors = <32>; }; |