Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 PCIe Endpoint controller maintainers: - Lucas Stach <l.stach@pengutronix.de> - Richard Zhu <hongxing.zhu@nxp.com> description: |+ This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. The controller instances are dual mode where in they can work either in Root Port mode or Endpoint mode but one at a time. properties: compatible: enum: - fsl,imx8mm-pcie-ep - fsl,imx8mq-pcie-ep - fsl,imx8mp-pcie-ep - fsl,imx95-pcie-ep clocks: minItems: 3 items: - description: PCIe bridge clock. - description: PCIe bus clock. - description: PCIe PHY clock. - description: Additional required clock entry for imx6sx-pcie, imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep. clock-names: minItems: 3 maxItems: 4 interrupts: items: - description: builtin eDMA interrupter. interrupt-names: items: - const: dma required: - compatible - reg - reg-names - interrupts - interrupt-names allOf: - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# - if: properties: compatible: enum: - fsl,imx8mm-pcie-ep - fsl,imx8mq-pcie-ep - fsl,imx8mp-pcie-ep then: properties: reg: minItems: 2 maxItems: 2 reg-names: items: - const: dbi - const: addr_space - if: properties: compatible: enum: - fsl,imx95-pcie-ep then: properties: reg: minItems: 6 maxItems: 6 reg-names: items: - const: dbi - const: atu - const: dbi2 - const: app - const: dma - const: addr_space - if: properties: compatible: enum: - fsl,imx8mq-pcie-ep - fsl,imx95-pcie-ep then: properties: clocks: minItems: 4 clock-names: items: - const: pcie - const: pcie_bus - const: pcie_phy - const: pcie_aux else: properties: clocks: maxItems: 3 clock-names: items: - const: pcie - const: pcie_bus - const: pcie_aux unevaluatedProperties: false examples: - | #include <dt-bindings/clock/imx8mp-clock.h> #include <dt-bindings/power/imx8mp-power.h> #include <dt-bindings/reset/imx8mp-reset.h> #include <dt-bindings/interrupt-controller/arm-gic.h> pcie_ep: pcie-ep@33800000 { compatible = "fsl,imx8mp-pcie-ep"; reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; reg-names = "dbi", "addr_space"; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_ROOT>; clock-names = "pcie", "pcie_bus", "pcie_aux"; assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; assigned-clock-rates = <10000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; num-lanes = <1>; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ interrupt-names = "dma"; fsl,max-link-speed = <3>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; reset-names = "apps", "turnoff"; phys = <&pcie_phy>; phy-names = "pcie-phy"; num-ib-windows = <4>; num-ob-windows = <4>; }; |