Documentation / devicetree / bindings / pci / rcar-pci-ep.yaml


Based on kernel version 6.10. Page generated on 2024-07-16 09:00 EST.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car PCIe Endpoint

maintainers:
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a774a1-pcie-ep     # RZ/G2M
          - renesas,r8a774b1-pcie-ep     # RZ/G2N
          - renesas,r8a774c0-pcie-ep     # RZ/G2E
          - renesas,r8a774e1-pcie-ep     # RZ/G2H
          - renesas,r8a7795-pcie-ep      # R-Car H3
      - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2

  reg:
    maxItems: 5

  reg-names:
    items:
      - const: apb-base
      - const: memory0
      - const: memory1
      - const: memory2
      - const: memory3

  interrupts:
    minItems: 3
    maxItems: 3

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: pcie

  max-functions:
    minimum: 1
    maximum: 1

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - resets
  - power-domains
  - clocks
  - clock-names
  - max-functions

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a774c0-sysc.h>
 
     pcie0_ep: pcie-ep@fe000000 {
            compatible = "renesas,r8a774c0-pcie-ep",
                         "renesas,rcar-gen3-pcie-ep";
            reg = <0xfe000000 0x80000>,
                  <0xfe100000 0x100000>,
                  <0xfe200000 0x200000>,
                  <0x30000000 0x8000000>,
                  <0x38000000 0x8000000>;
            reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
            interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
            resets = <&cpg 319>;
            power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
            clocks = <&cpg CPG_MOD 319>;
            clock-names = "pcie";
            max-functions = /bits/ 8 <1>;
    };