Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel Keem Bay PCIe controller Root Complex mode maintainers: - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> - Srikanth Thokala <srikanth.thokala@intel.com> allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: const: intel,keembay-pcie ranges: maxItems: 1 reset-gpios: maxItems: 1 reg: maxItems: 4 reg-names: items: - const: dbi - const: atu - const: config - const: apb clocks: maxItems: 2 clock-names: items: - const: master - const: aux interrupts: maxItems: 3 interrupt-names: items: - const: pcie - const: pcie_ev - const: pcie_err num-lanes: description: Number of lanes to use. enum: [ 1, 2 ] required: - compatible - reg - reg-names - ranges - clocks - clock-names - interrupts - interrupt-names - reset-gpios unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #define KEEM_BAY_A53_PCIE #define KEEM_BAY_A53_AUX_PCIE pcie@37000000 { compatible = "intel,keembay-pcie"; reg = <0x37000000 0x00001000>, <0x37300000 0x00001000>, <0x36e00000 0x00200000>, <0x37800000 0x00000200>; reg-names = "dbi", "atu", "config", "apb"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pcie", "pcie_ev", "pcie_err"; clocks = <&scmi_clk KEEM_BAY_A53_PCIE>, <&scmi_clk KEEM_BAY_A53_AUX_PCIE>; clock-names = "master", "aux"; reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>; num-lanes = <2>; }; |