Documentation / devicetree / bindings / pci / intel,keembay-pcie-ep.yaml


Based on kernel version 6.10. Page generated on 2024-07-16 09:00 EST.

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Keem Bay PCIe controller Endpoint mode

maintainers:
  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
  - Srikanth Thokala <srikanth.thokala@intel.com>

properties:
  compatible:
    const: intel,keembay-pcie-ep

  reg:
    maxItems: 5

  reg-names:
    items:
      - const: dbi
      - const: dbi2
      - const: atu
      - const: addr_space
      - const: apb

  interrupts:
    maxItems: 4

  interrupt-names:
    items:
      - const: pcie
      - const: pcie_ev
      - const: pcie_err
      - const: pcie_mem_access

  num-lanes:
    description: Number of lanes to use.
    enum: [ 1, 2 ]

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    pcie-ep@37000000 {
          compatible = "intel,keembay-pcie-ep";
          reg = <0x37000000 0x00001000>,
                <0x37100000 0x00001000>,
                <0x37300000 0x00001000>,
                <0x36000000 0x01000000>,
                <0x37800000 0x00000200>;
          reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
          interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
                       <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
                       <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
                       <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
          interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
          num-lanes = <2>;
    };