Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel Keem Bay PCIe controller Endpoint mode maintainers: - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> - Srikanth Thokala <srikanth.thokala@intel.com> properties: compatible: const: intel,keembay-pcie-ep reg: maxItems: 5 reg-names: items: - const: dbi - const: dbi2 - const: atu - const: addr_space - const: apb interrupts: maxItems: 4 interrupt-names: items: - const: pcie - const: pcie_ev - const: pcie_err - const: pcie_mem_access num-lanes: description: Number of lanes to use. enum: [ 1, 2 ] required: - compatible - reg - reg-names - interrupts - interrupt-names additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> pcie-ep@37000000 { compatible = "intel,keembay-pcie-ep"; reg = <0x37000000 0x00001000>, <0x37100000 0x00001000>, <0x37300000 0x00001000>, <0x36000000 0x01000000>, <0x37800000 0x00000200>; reg-names = "dbi", "dbi2", "atu", "addr_space", "apb"; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access"; num-lanes = <2>; }; |