Documentation / devicetree / bindings / pci / sifive,fu740-pcie.yaml


Based on kernel version 6.10. Page generated on 2024-07-16 09:00 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive FU740 PCIe host controller

description: |+
  SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
  PCI core. It shares common features with the PCIe DesignWare core and
  inherits common properties defined in
  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.

maintainers:
  - Paul Walmsley <paul.walmsley@sifive.com>
  - Greentime Hu <greentime.hu@sifive.com>

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    const: sifive,fu740-pcie

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: dbi
      - const: config
      - const: mgmt

  dma-coherent: true

  num-lanes:
    const: 8

  msi-parent: true

  interrupt-names:
    items:
      - const: msi
      - const: inta
      - const: intb
      - const: intc
      - const: intd

  resets:
    description: A phandle to the PCIe power up reset line.
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: pcie_aux

  pwren-gpios:
    description: Should specify the GPIO for controlling the PCI bus device power on.
    maxItems: 1

  reset-gpios:
    maxItems: 1

required:
  - dma-coherent
  - num-lanes
  - interrupts
  - interrupt-names
  - interrupt-map-mask
  - interrupt-map
  - clocks
  - clock-names
  - resets
  - pwren-gpios
  - reset-gpios

unevaluatedProperties: false

examples:
  - |
    bus {
        #address-cells = <2>;
        #size-cells = <2>;
        #include <dt-bindings/clock/sifive-fu740-prci.h>
 
        pcie@e00000000 {
            compatible = "sifive,fu740-pcie";
            #address-cells = <3>;
            #size-cells = <2>;
            #interrupt-cells = <1>;
            reg = <0xe 0x00000000 0x0 0x80000000>,
                  <0xd 0xf0000000 0x0 0x10000000>,
                  <0x0 0x100d0000 0x0 0x1000>;
            reg-names = "dbi", "config", "mgmt";
            device_type = "pci";
            dma-coherent;
            bus-range = <0x0 0xff>;
            ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000>,      /* I/O */
                     <0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000>,    /* mem */
                     <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000>,    /* mem */
                     <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
            num-lanes = <0x8>;
            interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
            interrupt-names = "msi", "inta", "intb", "intc", "intd";
            interrupt-parent = <&plic0>;
            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
            interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
                            <0x0 0x0 0x0 0x2 &plic0 58>,
                            <0x0 0x0 0x0 0x3 &plic0 59>,
                            <0x0 0x0 0x0 0x4 &plic0 60>;
            clock-names = "pcie_aux";
            clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
            resets = <&prci 4>;
            pwren-gpios = <&gpio 5 0>;
            reset-gpios = <&gpio 8 0>;
        };
    };