Based on kernel version 6.10
. Page generated on 2024-07-16 09:00 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SC7280 PCI Express Root Complex maintainers: - Bjorn Andersson <andersson@kernel.org> - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> description: Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys DesignWare PCIe IP. properties: compatible: const: qcom,pcie-sc7280 reg: minItems: 5 maxItems: 6 reg-names: minItems: 5 items: - const: parf # Qualcomm specific registers - const: dbi # DesignWare PCIe registers - const: elbi # External local bus interface registers - const: atu # ATU address space - const: config # PCIe configuration space - const: mhi # MHI registers clocks: minItems: 13 maxItems: 13 clock-names: items: - const: pipe # PIPE clock - const: pipe_mux # PIPE MUX - const: phy_pipe # PIPE output clock - const: ref # REFERENCE clock - const: aux # Auxiliary clock - const: cfg # Configuration clock - const: bus_master # Master AXI clock - const: bus_slave # Slave AXI clock - const: slave_q2a # Slave Q2A clock - const: tbu # PCIe TBU clock - const: ddrss_sf_tbu # PCIe SF TBU clock - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock - const: aggre1 # Aggre NoC PCIe1 AXI clock interrupts: maxItems: 1 interrupt-names: items: - const: msi resets: maxItems: 1 reset-names: items: - const: pci vddpe-3v3-supply: description: PCIe endpoint power supply allOf: - $ref: qcom,pcie-common.yaml# unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,gcc-sc7280.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> soc { #address-cells = <2>; #size-cells = <2>; pcie@1c08000 { compatible = "qcom,pcie-sc7280"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, <0 0x40001000 0 0x1000>, <0 0x40100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; bus-range = <0x00 0xff>; device_type = "pci"; linux,pci-domain = <1>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, <&pcie1_phy>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, <&gcc GCC_DDRSS_PCIE_SF_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; clock-names = "pipe", "pipe_mux", "phy_pipe", "ref", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "tbu", "ddrss_sf_tbu", "aggre0", "aggre1"; dma-coherent; interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, <0x100 &apps_smmu 0x1c81 0x1>; phys = <&pcie1_phy>; phy-names = "pciephy"; pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; power-domains = <&gcc GCC_PCIE_1_GDSC>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pp3300_ssd>; }; }; |