Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 | * Axis ARTPEC-6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. Required properties: - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; - reg: base addresses and lengths of the PCIe controller (DBI), the PHY controller, and configuration address space. - reg-names: Must include the following entries: - "dbi" - "phy" - "config" - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. - interrupt-names: Must include the following entries: - "msi": The interrupt that is asserted when an MSI is received - axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller, used to enable and control the Synopsys IP. Example: pcie@f8050000 { compatible = "axis,artpec6-pcie", "snps,dw-pcie"; reg = <0xf8050000 0x2000 0xf8040000 0x1000 0xc0000000 0x2000>; reg-names = "dbi", "phy", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; /* downstream I/O */ ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 /* non-prefetchable memory */ 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; num-lanes = <2>; bus-range = <0x00 0xff>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; axis,syscon-pcie = <&syscon>; }; |