Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Baikal-T1 PCIe Root Port Controller maintainers: - Serge Semin <fancer.lancer@gmail.com> description: Embedded into Baikal-T1 SoC Root Complex controller with a single port activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured to have just a single Root Port function and is capable of establishing the link up to Gen.3 speed on x4 lanes. It doesn't have embedded clock and reset control module, so the proper interface initialization is supposed to be performed by software. There four in- and four outbound iATU regions which can be used to emit all required TLP types on the PCIe bus. allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# properties: compatible: const: baikal,bt1-pcie reg: description: DBI, DBI2 and at least 4KB outbound iATU-capable region for the peripheral devices CFG-space access. maxItems: 3 reg-names: items: - const: dbi - const: dbi2 - const: config interrupts: description: MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization request and eight Read/Write eDMA IRQ lines are available. maxItems: 14 interrupt-names: items: - const: dma0 - const: dma1 - const: dma2 - const: dma3 - const: dma4 - const: dma5 - const: dma6 - const: dma7 - const: msi - const: aer - const: pme - const: hp - const: bw_mg - const: l_eq clocks: description: DBI (attached to the APB bus), AXI-bus master and slave interfaces are fed up by the dedicated application clocks. A common reference clock signal is supposed to be attached to the corresponding Ref-pad of the SoC. It will be redistributed amongst the controller core sub-modules (pipe, core, aux, etc). maxItems: 4 clock-names: items: - const: dbi - const: mstr - const: slv - const: ref resets: description: A comprehensive controller reset logic is supposed to be implemented by software, so almost all the possible application and core reset signals are exposed via the system CCU module. maxItems: 9 reset-names: items: - const: mstr - const: slv - const: pwr - const: hot - const: phy - const: core - const: pipe - const: sticky - const: non-sticky baikal,bt1-syscon: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the Baikal-T1 System Controller DT node. It's required to access some additional PM, Reset-related and LTSSM signals. num-lanes: maximum: 4 max-link-speed: maximum: 3 required: - compatible - reg - reg-names - interrupts - interrupt-names unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/mips-gic.h> #include <dt-bindings/gpio/gpio.h> pcie@1f052000 { compatible = "baikal,bt1-pcie"; device_type = "pci"; reg = <0x1f052000 0x1000>, <0x1f053000 0x1000>, <0x1bdbf000 0x1000>; reg-names = "dbi", "dbi2", "config"; #address-cells = <3>; #size-cells = <2>; ranges = <0x81000000 0 0x00000000 0x1bdb0000 0 0x00008000>, <0x82000000 0 0x20000000 0x08000000 0 0x13db0000>; bus-range = <0x0 0xff>; interrupts = <GIC_SHARED 80 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 81 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 82 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 83 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 85 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 86 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 87 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 93 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7", "msi", "aer", "pme", "hp", "bw_mg", "l_eq"; clocks = <&ccu_sys 1>, <&ccu_axi 6>, <&ccu_axi 7>, <&clk_pcie>; clock-names = "dbi", "mstr", "slv", "ref"; resets = <&ccu_axi 6>, <&ccu_axi 7>, <&ccu_sys 7>, <&ccu_sys 10>, <&ccu_sys 4>, <&ccu_sys 6>, <&ccu_sys 5>, <&ccu_sys 8>, <&ccu_sys 9>; reset-names = "mstr", "slv", "pwr", "hot", "phy", "core", "pipe", "sticky", "non-sticky"; reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>; num-lanes = <4>; max-link-speed = <3>; }; ... |