Based on kernel version 6.11
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Gen3 PCIe controller on MediaTek SoCs maintainers: - Jianjun Wang <jianjun.wang@mediatek.com> description: |+ PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed and compatible with Gen2, Gen1 speed. This PCIe controller supports up to 256 MSI vectors, the MSI hardware block diagram is as follows: +-----+ | GIC | +-----+ ^ | port->irq | +-+-+-+-+-+-+-+-+ |0|1|2|3|4|5|6|7| (PCIe intc) +-+-+-+-+-+-+-+-+ ^ ^ ^ | | ... | +-------+ +------+ +-----------+ | | | +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ | | | | | | | | | | | | (MSI vectors) | | | | | | | | | | | | (MSI SET0) (MSI SET1) ... (MSI SET7) With 256 MSI vectors supported, the MSI vectors are composed of 8 sets, each set has its own address for MSI message, and supports 32 MSI vectors to generate interrupt. properties: compatible: oneOf: - items: - enum: - mediatek,mt7986-pcie - mediatek,mt8188-pcie - mediatek,mt8195-pcie - const: mediatek,mt8192-pcie - const: mediatek,mt8192-pcie reg: maxItems: 1 reg-names: items: - const: pcie-mac interrupts: maxItems: 1 ranges: minItems: 1 maxItems: 8 iommu-map: maxItems: 1 iommu-map-mask: const: 0 resets: minItems: 1 maxItems: 2 reset-names: minItems: 1 maxItems: 2 items: enum: [ phy, mac ] clocks: minItems: 4 maxItems: 6 clock-names: minItems: 4 maxItems: 6 assigned-clocks: maxItems: 1 assigned-clock-parents: maxItems: 1 phys: maxItems: 1 phy-names: items: - const: pcie-phy power-domains: maxItems: 1 '#interrupt-cells': const: 1 interrupt-controller: description: Interrupt controller node for handling legacy PCI interrupts. type: object properties: '#address-cells': const: 0 '#interrupt-cells': const: 1 interrupt-controller: true required: - '#address-cells' - '#interrupt-cells' - interrupt-controller additionalProperties: false required: - compatible - reg - reg-names - interrupts - ranges - clocks - clock-names - '#interrupt-cells' - interrupt-controller allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# - if: properties: compatible: const: mediatek,mt8192-pcie then: properties: clock-names: items: - const: pl_250m - const: tl_26m - const: tl_96m - const: tl_32k - const: peri_26m - const: top_133m - if: properties: compatible: contains: enum: - mediatek,mt8188-pcie - mediatek,mt8195-pcie then: properties: clock-names: items: - const: pl_250m - const: tl_26m - const: tl_96m - const: tl_32k - const: peri_26m - const: peri_mem - if: properties: compatible: contains: enum: - mediatek,mt7986-pcie then: properties: clock-names: items: - const: pl_250m - const: tl_26m - const: peri_26m - const: top_133m unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> bus { #address-cells = <2>; #size-cells = <2>; pcie: pcie@11230000 { compatible = "mediatek,mt8192-pcie"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; reg = <0x00 0x11230000 0x00 0x4000>; reg-names = "pcie-mac"; interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; bus-range = <0x00 0xff>; ranges = <0x82000000 0x00 0x12000000 0x00 0x12000000 0x00 0x1000000>; clocks = <&infracfg 44>, <&infracfg 40>, <&infracfg 43>, <&infracfg 97>, <&infracfg 99>, <&infracfg 111>; clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", "peri_26m", "top_133m"; assigned-clocks = <&topckgen 50>; assigned-clock-parents = <&topckgen 91>; phys = <&pciephy>; phy-names = "pcie-phy"; resets = <&infracfg_rst 2>, <&infracfg_rst 3>; reset-names = "phy", "mac"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc 0>, <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; pcie_intc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; }; |