Based on kernel version 6.18. Page generated on 2025-12-02 09:03 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper) description: Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core. maintainers: - Chen Wang <unicorn_wang@outlook.com> properties: compatible: const: sophgo,sg2042-pcie-host reg: maxItems: 2 reg-names: items: - const: reg - const: cfg vendor-id: const: 0x1f1c device-id: const: 0x2042 msi-parent: true allOf: - $ref: cdns-pcie-host.yaml# required: - compatible - reg - reg-names unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> pcie@62000000 { compatible = "sophgo,sg2042-pcie-host"; device_type = "pci"; reg = <0x62000000 0x00800000>, <0x48000000 0x00001000>; reg-names = "reg", "cfg"; #address-cells = <3>; #size-cells = <2>; ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; bus-range = <0x00 0xff>; vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; msi-parent = <&msi>; }; |