Based on kernel version 7.3. Page generated on 2026-10-19 13:17 EDT.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/spi/nuvoton,ma35d1-qspi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Nuvoton MA35D1 Quad SPI Controller maintainers: - Chi-Wen Weng <cwweng@nuvoton.com> allOf: - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: const: nuvoton,ma35d1-qspi reg: maxItems: 1 interrupts: maxItems: 1 clocks: maxItems: 1 resets: maxItems: 1 num-cs: minimum: 1 maximum: 2 default: 2 cs-gpios: false required: - compatible - reg - clocks - resets unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> #include <dt-bindings/reset/nuvoton,ma35d1-reset.h> soc { #address-cells = <2>; #size-cells = <2>; spi@40680000 { compatible = "nuvoton,ma35d1-qspi"; reg = <0 0x40680000 0 0x100>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk QSPI0_GATE>; resets = <&sys MA35D1_RESET_QSPI0>; #address-cells = <1>; #size-cells = <0>; }; }; |