Based on kernel version 6.17
. Page generated on 2025-10-03 10:04 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/spi/marvell,orion-spi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Marvell Orion SPI controller maintainers: - Andrew Lunn <andrew@lunn.ch> - Gregory CLEMENT <gregory.clement@bootlin.com> allOf: - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: oneOf: - enum: - marvell,orion-spi - marvell,armada-380-spi # For ap80x and cp11x - items: - enum: - marvell,armada-370-spi - marvell,armada-375-spi - marvell,armada-380-spi - marvell,armada-390-spi - marvell,armada-xp-spi - const: marvell,orion-spi cell-index: description: Instance id for the SPI controller deprecated: true reg: minItems: 1 items: - description: control registers - description: CS0 MBUS target/attribute registers for direct mode - description: CS1 MBUS target/attribute registers for direct mode - description: CS2 MBUS target/attribute registers for direct mode - description: CS3 MBUS target/attribute registers for direct mode - description: CS4 MBUS target/attribute registers for direct mode - description: CS5 MBUS target/attribute registers for direct mode - description: CS6 MBUS target/attribute registers for direct mode - description: CS7 MBUS target/attribute registers for direct mode clocks: minItems: 1 maxItems: 2 clock-names: items: - const: core - const: axi interrupts: maxItems: 1 required: - compatible - reg - clocks unevaluatedProperties: false examples: - | spi@10600 { compatible = "marvell,orion-spi"; #address-cells = <1>; #size-cells = <0>; cell-index = <0>; reg = <0x10600 0x28>; clocks = <&coreclk 0>; interrupts = <23>; }; - | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) bus { #address-cells = <2>; #size-cells = <1>; spi@10600 { compatible = "marvell,orion-spi"; #address-cells = <1>; #size-cells = <0>; cell-index = <0>; reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */ <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */ <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */ <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */ <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */ <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */ <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */ <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */ <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */ clocks = <&coreclk 0>; interrupts = <23>; }; }; |