Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 | Lantiq Synchronous Serial Controller (SSC) SPI master driver Required properties: - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi", "intel,lgm-spi" - #address-cells: see spi-bus.txt - #size-cells: see spi-bus.txt - reg: address and length of the spi master registers - interrupts: For compatible "intel,lgm-ssc" - the common interrupt number for all of tx rx & err interrupts. or For rest of the compatibles, should contain the "spi_rx", "spi_tx" and "spi_err" interrupt. Optional properties: - clocks: spi clock phandle - num-cs: see spi-bus.txt, set to 8 if unset - base-cs: the number of the first chip select, set to 1 if unset. Example: spi: spi@e100800 { compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi"; reg = <0xE100800 0x100>; interrupt-parent = <&icu0>; interrupts = <22 23 24>; interrupt-names = "spi_rx", "spi_tx", "spi_err"; #address-cells = <1>; #size-cells = <1>; num-cs = <6>; base-cs = <1>; }; ssc0: spi@e0800000 { compatible = "intel,lgm-spi"; reg = <0xe0800000 0x400>; interrupt-parent = <&ioapic1>; interrupts = <35 1>; #address-cells = <1>; #size-cells = <0>; clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>; clock-names = "freq", "gate"; }; |