Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) # Copyright 2020-21 Cadence %YAML 1.2 --- $id: http://devicetree.org/schemas/spi/cdns,xspi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence XSPI Controller maintainers: - Parshuram Thombare <pthombar@cadence.com> description: | The XSPI controller allows SPI protocol communication in single, dual, quad or octal wire transmission modes for read/write access to slaves such as SPI-NOR flash. allOf: - $ref: spi-controller.yaml# properties: compatible: const: cdns,xspi-nor reg: items: - description: address and length of the controller register set - description: address and length of the Slave DMA data port - description: address and length of the auxiliary registers reg-names: items: - const: io - const: sdma - const: aux interrupts: maxItems: 1 required: - compatible - reg - interrupts unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> bus { #address-cells = <2>; #size-cells = <2>; xspi: spi@a0010000 { #address-cells = <1>; #size-cells = <0>; compatible = "cdns,xspi-nor"; reg = <0x0 0xa0010000 0x0 0x1040>, <0x0 0xb0000000 0x0 0x1000>, <0x0 0xa0020000 0x0 0x100>; reg-names = "io", "sdma", "aux"; interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <75000000>; reg = <0>; }; flash@1 { compatible = "jedec,spi-nor"; spi-max-frequency = <75000000>; reg = <1>; }; }; }; |